Field
The present invention relates to integrated circuit memory, and more specifically to technology for accurately sensing data stored in large-scale memory arrays.
Description of Related Art
The size of memory arrays in integrated circuit memory devices has been steadily increasing. As a result, a single bit line in a large-scale memory array can be coupled with a very large number of individual memory cells. During sensing of data from a selected memory cell, unselected memory cells coupled to the bit line can contribute leakage current that can interfere with the operation of the sensing circuitry. As the number of unselected memory cells increases, the contributions of leakage current adds up and reduces the sensing margin available for the array.
One type of memory array in which this problem is encountered includes programmable resistance memory devices with a high density array of cells organized in a cross-point architecture, such as described in U.S. Pat. No. 6,579,760, entitled SELF-ALIGNED, PROGRAMMABLE PHASE CHANGE MEMORY, issued 17 Jun. 2003, by Lung. Cross-point architectures with memory cells that include a phase change memory element in series with an ovonic threshold switch have been developed as well. Other architectures are utilized, including a variety of 2-dimensional and 3-dimensional array structures. Even in an off state, programmable resistive memory cells can conduct small amounts of leakage current that adds up. Thus, compensation for the leakage current in such devices has been explored. See, U.S. Pat. No. 7,245,526, entitled PHASE CHANGE MEMORY DEVICE PROVIDING COMPENSATION FOR LEAKAGE CURRENT, issued 17 Jul. 2007, by Oh et al.
Similar leakage current problems arise in other memory architectures, including for example NOR flash architectures.
It is desirable to provide technology that can compensate for this leakage effect, and improve the read margin in high density memory arrays.